Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 163
© 2012 Broadcom Corporation. All rights reserved
2 TXDMAPREQ Unsupported, write zero, read as don't care RO 0x0
1 UE TXUE TX Underrun Error
0 - No error case detected
1 Set when TX FIFO is empty and I2C master
attempt to read a data character from I2C slave.
Cleared by writing 0 to it.
RW 0x0
0 OE RXOE RX Overrun Error
0 No error case detected
1 Set when RX FIFO is full and a new data
character is received. Cleared by writing 0 to it.
RW 0x0
SLV Register
Synopsis
The I2C SPI Address Register holds the I2C slave address value. NOTE: It is of no
use in SPI mode.
Bit(s)
Field Name
Description
Type
Reset
31:7
Reserved
-
Write as 0, read as don't care
6:0 ADDR SLVADDR I2C Slave Address
Programmable I2C slave address
Note: In case HOSTCTRLEN bit is set from the
I2C SPI Control Register bit SLVADDR[0]
chooses the following:
0 - selects normal operation, i.e. accessing RX
and TX FIFOs.
1 - selects access to I2C SPI SW Status
Register or I2C SPI Host Control Register
RW 0x0
CR Register
Synopsis
The Control register is used to configure the I2C or SPI operation.
Bit(s)
Field Name
Description
Type
Reset
31:14
Reserved
-
Write as 0, read as don't care