Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 162
© 2012 Broadcom Corporation. All rights reserved
18 TXFF TXFF TX FIFO Full
0 TX FIFO is not full
1 When TX FIFO is full
RO 0x0
17 RXFE RXFE RX FIFO Empty
0 FX FIFO is not empty
1 When FX FIFO is empty
RO 0x1
16 TXBUSY TXBUSY Transmit Busy
0 Transmit operation inactive
1 Transmit operation in operation
RO 0x0
15:10
Reserved
-
Write as 0, read as don't care
9 UE TXUE TX Underrun Error
0 - No error case detected
1 Set when TX FIFO is empty and I2C master
attempt to read a data character from I2C slave.
Cleared by writing 0 to I2C SPI Status register .
RO 0x0
8 OE RXOE RX Overrun Error
0 No error case detected
1 Set when RX FIFO is full and a new data
character is received. Cleared by writing 0 to I2C
SPI Status register .
RO 0x0
7:0 DATA DATA Received/Transferred data characters
Data written to this location is pushed into the TX
FIFO.
Data read from this location is fetched from the
RX FIFO.
RW 0x0
RSR Register
Synopsis
The operation status register and error clear register.
Bit(s)
Field Name
Description
Type
Reset
31:6
Reserved
-
Write as 0, read as don't care
5 RXDMABREQ Unsupported, write zero, read as don't care RO 0x0
4 RXDMAPREQ Unsupported, write zero, read as don't care RO 0x0
3 TXDMABREQ Unsupported, write zero, read as don't care RO 0x0