Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 161
© 2012 Broadcom Corporation. All rights reserved
0x1c
RIS
Raw Interupt Status Register 32
0x20
MIS
Masked Interupt Status Register 32
0x24
ICR
Interupt Clear Register 32
0x28
DMACR
DMA Control Register 32
0x2c
TDR
FIFO Test Data 32
0x30
GPUSTAT
GPU Status Register 32
0x34
HCTRL
Host Control Register 32
0x38
DEBUG1
I2C Debug Register 32
0x3c
DEBUG2
SPI Debug Register 32
DR Register
Synopsis
The I2C SPI Data Register is used to transfer/receive data characters and provide a
Status and Flag information. Status and Flag information is also available via individual
registers.
Bit(s)
Field Name
Description
Type
Reset
31:27 RXFLEVEL RXFLEVEL RX FIFO Level
Returns the current level of the RX FIFO use
RO 0x0
26:22 TXFLEVEL TXFLEVEL TX FIFO Level
Returns the current level of the TX FIFO use
RO 0x0
21 RXBUSY RXBUSY Receive Busy
0 Receive operation inactive
1 Receive operation in operation
RO 0x0
20 TXFE TXFE TX FIFO Empty
0 TX FIFO is not empty
1 When TX FIFO is empty
RO 0x1
19 RXFF RXFE RX FIFO Full
0 FX FIFO is not full
1 When FX FIFO is full
RO 0x0