Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 159
© 2012 Broadcom Corporation. All rights reserved
10.6.4 Notes
1. The SPI Master knows nothing of the peripherals it is connected to. It always both
sends and receives bytes for every byte of the transaction.
2. SCLK is only generated during byte serial transfer. It pauses in the rest state if the
next byte to send is not ready or RXF is set.
3. Setup and Hold times related to the automatic assertion and de-assertion of the CS lines
when operating in DMA mode (DMAEN and ADCS set) are as follows:
The CS line will be asserted at least 3 core clock cycles before the msb of the first byte of the
transfer.
The CS line will be de-asserted no earlier than 1 core clock cycle after the trailing edge of the
final clock pulse.
If these parameters are insufficient, software control should alleviate the problem. ADCS
should be 0 allowing software to manually control the assertion and de-assertion of the CS
lines.