Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 157
© 2012 Broadcom Corporation. All rights reserved
LTOH Register
Synopsis
This register allows the LoSSI output hold delay to be set.
Bit(s)
Field Name
Description
Type
Reset
31:4
Reserved
-
Write as 0, read as don't care
3:0 TOH This sets the Output Hold delay in APB clocks. A
value of 0 causes a 1 clock delay.
RW 0x1
DC Register
Synopsis
This register controls the generation of the DREQ and Panic signals to an external
DMA engine The DREQ signals are generated when the FIFOs reach their defined
levels and need servicing. The Panic signals instruct the external DMA engine to raise
the priority of its AXI requests.
Bit(s)
Field Name
Description
Type
Reset
31:24 RPANIC DMA Read Panic Threshold.
Generate the Panic signal to the RX DMA
engine whenever the RX FIFO level is greater
than this amount.
RW 0x30
23:16 RDREQ DMA Read Request Threshold.
Generate A DREQ to the RX DMA engine
whenever the RX FIFO level is greater than this
amount, (RX DREQ is also generated if the
transfer has finished but the RXFIFO isn t
empty).
RW 0x20
15:8 TPANIC DMA Write Panic Threshold.
Generate the Panic signal to the TX DMA engine
whenever the TX FIFO level is less than or equal
to this amount.
RW 0x10
7:0 TDREQ DMA Write Request Threshold.
Generate a DREQ signal to the TX DMA engine
whenever the TX FIFO level is less than or equal
to this amount.
RW 0x20