Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 154
© 2012 Broadcom Corporation. All rights reserved
18 TXD TXD TX FIFO can accept Data
0 = TX FIFO is full and so cannot accept more
data.
1 = TX FIFO has space for at least 1 byte.
RO 0x1
17 RXD RXD RX FIFO contains Data
0 = RX FIFO is empty.
1 = RX FIFO contains at least 1 byte.
RO 0x0
16 DONE Done transfer Done
0 = Transfer is in progress (or not active TA = 0).
1 = Transfer is complete. Cleared by writing
more data to the TX FIFO or setting TA to 0.
RO 0x0
15 TE_EN Unused RW 0x0
14 LMONO Unused RW 0x0
13 LEN LEN LoSSI enable
The serial interface is configured as a LoSSI
master.
0 = The serial interface will behave as an SPI
master.
1 = The serial interface will behave as a LoSSI
master.
RW 0x0
12 REN REN Read Enable
read enable if you are using bidirectional mode.
If this bit is set, the SPI peripheral will be able to
send data to this device.
0 = We intend to write to the SPI peripheral.
1 = We intend to read from the SPI peripheral.
RW 0x1
11 ADCS ADCS Automatically Deassert Chip Select
0 = Don t automatically deassert chip select at
the end of a DMA transfer chip select is
manually controlled by software.
1 = Automatically deassert chip select at the end
of a DMA transfer (as determined by SPIDLEN)
RW 0x0
10 INTR INTR Interrupt on RXR
0 = Don t generate interrupts on RX FIFO
condition.
1 = Generate interrupt while RXR = 1.
RW 0x0
9 INTD INTD Interrupt on Done
0 = Don t generate interrupt on transfer
complete.
1 = Generate interrupt when DONE = 1.
RW 0x0