Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 153
© 2012 Broadcom Corporation. All rights reserved
0xc
DLEN
SPI Master Data Length 32
0x10
LTOH
SPI LOSSI mode TOH 32
0x14
DC
SPI DMA DREQ Controls 32
CS Register
Synopsis
This register contains the main control and status bits for the SPI.
Bit(s)
Field Name
Description
Type
Reset
31:26
Reserved
-
Write as 0, read as don't care
25 LEN_LONG Enable Long data word in Lossi mode if
DMA_LEN is set
0= writing to the FIFO will write a single byte
1= wrirng to the FIFO will write a 32 bit word
RW 0x0
24 DMA_LEN Enable DMA mode in Lossi mode RW 0x0
23 CSPOL2 Chip Select 2 Polarity
0= Chip select is active low.
1= Chip select is active high.
RW 0x0
22 CSPOL1 Chip Select 1 Polarity
0= Chip select is active low.
1= Chip select is active high.
RW 0x0
21 CSPOL0 Chip Select 0 Polarity
0= Chip select is active low.
1= Chip select is active high.
RW 0x0
20 RXF RXF - RX FIFO Full
0 = RXFIFO is not full.
1 = RX FIFO is full. No further serial data will be
sent/ received until data is read from FIFO.
RO 0x0
19 RXR RXR RX FIFO needs Reading ( full)
0 = RX FIFO is less than full (or not active TA =
0).
1 = RX FIFO is or more full. Cleared by reading
sufficient data from the RX FIFO or setting TA to
0.
RO 0x0