Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 15
© 2012 Broadcom Corporation. All rights reserved
AUX_MU_LSR_REG Register (0x7E21 5054)
S
YNOPSIS The AUX_MU_LSR_REG register shows the data status.
Bit(s) Field Name Description Type Reset
31:8
Reserved, write zero, read as don’t care
7
Reserved, write zero, read as don’t care
This bit has a function in a 16550 compatible UART
but is ignored here
0
6
Transmitter
idle
This bit is set if the transmit FIFO is empty and the
transmitter is idle. (Finished shifting out the last bit).
R 1
5
Transmitter
empty
This bit is set if the transmit FIFO can accept at least
one byte.
R 0
4:2
Reserved, write zero, read as don’t care
Some of these bits have functions in a 16550
compatible UART but are ignored here
0
1
Receiver
Overrun
This bit is set if there was a receiver overrun. That is:
one or more characters arrived whilst the receive
FIFO was full. The newly arrived charters have been
discarded. This bit is cleared each time this register is
read. To do a non-destructive read of this overrun bit
use the Mini Uart Extra Status register.
R/C 0
0 Data ready
This bit is set if the receive FIFO holds at least 1
symbol.
R 0
AUX_MU_MSR_REG Register (0x7E21 5058)
S
YNOPSIS The AUX_MU_MSR_REG register shows the 'modem' status.
Bit(s) Field Name Description Type Reset
31:8
Reserved, write zero, read as don’t care
7:6
Reserved, write zero, read as don’t care
Some of these bits have functions in a 16550
compatible UART but are ignored here
0
5 CTS status
This bit is the inverse of the UART1_CTS input Thus
:
If set the UART1_CTS pin is low
If clear the UART1_CTS pin is high
R 1
3:0
Reserved, write zero, read as don’t care
Some of these bits have functions in a 16550
compatible UART but are ignored here
0