Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 145
© 2012 Broadcom Corporation. All rights reserved
1 EMPT1 Fifo Empty Flag RW 0x1
0 FULL1 Fifo Full Flag RW 0x0
DMAC Register
Synopsis
ENAB bit is used to start DMA.
PANIC bits are used to determine the threshold level for PANIC signal going active.
Default value is 7.
DREQ bits are used to determine the threshold level for DREQ signal going active.
Default value is 7.
Bit(s)
Field Name
Description
Type
Reset
31 ENAB DMA Enable
0: DMA disabled
1: DMA enabled
RW 0x0
30:16
Reserved
-
Write as 0, read as don't care
15:8 PANIC DMA Threshold for PANIC signal RW 0x7
7:0 DREQ DMA Threshold for DREQ signal RW 0x7
RNG1 Register
Synopsis
This register is used to define the range for the corresponding channel. In PWM mode
evenly distributed pulses are sent within a period of length defined by this register. In
serial mode serialised data is transmitted within the same period. If the value in
PWM_RNGi is less than 32, only the first PWM_RNGi bits are sent resulting in a
truncation. If it is larger than 32 excess zero bits are padded at the end of data. Default
value for this register is 32.
Note: Channels 3 and 4 are not available in B0 and corresponding Channel Range
Registers are ignored.
Bit(s)
Field Name
Description
Type
Reset
31:0 PWM_RNGi Channel i Range RW 0x20