Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 144
© 2012 Broadcom Corporation. All rights reserved
STA Register
Synopsis
FULL1 bit indicates the full status of the FIFO. If this bit is high FIFO is full.
EMPT1 bit indicates the empty status of the FIFO. If this bit is high FIFO is empty.
WERR1 bit sets to high when a write when full error occurs. Software must clear this
bit by writing 1. Writing 0 to this bit has no effect.
RERR1 bit sets to high when a read when empty error occurs. Software must clear this
bit by writing 1. Writing 0 to this bit has no effect.
GAPOi. bit indicates that there has been a gap between transmission of two
consecutive data from FIFO. This may happen when FIFO gets empty after state
machine has sent a word and waits for the next. If control bit RPTLi is set to high this
event will not occur. Software must clear this bit by writing 1. Writing 0 to this bit has no
effect.
BERR sets to high when an error has occurred while writing to registers via APB. This
may happen if the bus tries to write successively to same set of registers faster than
the synchroniser block can cope with. Multiple switching may occur and contaminate
the data during synchronisation. Software should clear this bit by writing 1. Writing 0 to
this bit has no effect.
STAi bit indicates the current state of the channel which is useful for debugging
purposes. 0 means the channel is not currently transmitting. 1 means channel is
transmitting data.
Bit(s)
Field Name
Description
Type
Reset
31:13
Reserved
-
Write as 0, read as don't care
12 STA4 Channel 4 State RW 0x0
11 STA3 Channel 3 State RW 0x0
10 STA2 Channel 2 State RW 0x0
9 STA1 Channel 1 State RW 0x0
8 BERR Bus Error Flag RW 0x0
7 GAPO4 Channel 4 Gap Occurred Flag RW 0x0
6 GAPO3 Channel 3 Gap Occurred Flag RW 0x0
5 GAPO2 Channel 2 Gap Occurred Flag RW 0x0
4 GAPO1 Channel 1 Gap Occurred Flag RW 0x0
3 RERR1 Fifo Read Error Flag RW 0x0
2 WERR1 Fifo Write Error Flag RW 0x0