Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 143
© 2012 Broadcom Corporation. All rights reserved
10 RPTL2 Channel 1 Repeat Last Data
0: Transmission interrupts when FIFO is empty
1: Last data in FIFO is transmitted repetedly until
FIFO is not empty
RW 0x0
9 MODE2 Channel 1 Mode
0: PWM mode
1: Serialiser mode
RW 0x0
8 PWEN2 Channel 1 Enable
0: Channel is disabled
1: Channel is enabled
RW 0x0
7 MSEN1 Channel 1 M/S Enable
0: PWM algorithm is used
1: M/S transmission is used.
RW 0x0
6 CLRF1 Clear Fifo
1: Clears FIFO
0: Has no effect
This is a single shot operation. This bit always
reads 0
RO 0x0
5 USEF1 Channel 1 Use Fifo
0: Data register is transmitted
1: Fifo is used for transmission
RW 0x0
4 POLA1 Channel 1 Polarity
0 : 0=low 1=high
1: 1=low 0=high
RW 0x0
3 SBIT1 Channel 1 Silence Bit
Defines the state of the output when no
transmission takes place
RW 0x0
2 RPTL1 Channel 1 Repeat Last Data
0: Transmission interrupts when FIFO is empty
1: Last data in FIFO is transmitted repetedly until
FIFO is not empty
RW 0x0
1 MODE1 Channel 1 Mode
0: PWM mode
1: Serialiser mode
RW 0x0
0 PWEN1 Channel 1 Enable
0: Channel is disabled
1: Channel is enabled
RW 0x0