Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 142
© 2012 Broadcom Corporation. All rights reserved
Synopsis
PWENi is used to enable/disable the corresponding channel. Setting this bit to 1
enables the channel and transmitter state machine. All registers and FIFO is writable
without setting this bit.
MODEi bit is used to determine mode of operation. Setting this bit to 0 enables PWM
mode. In this mode data stored in either PWM_DATi or FIFO is transmitted by pulse
width modulation within the range defined by PWM_RNGi. When this mode is used
MSENi defines whether to use PWM algorithm. Setting MODEi to 1 enables serial
mode, in which data stored in either PWM_DATi or FIFO is transmitted serially within
the range defined by PWM_RNGi. Data is transmitted MSB first and truncated or zero-
padded depending on PWM_RNGi. Default mode is PWM.
RPTLi is used to enable/disable repeating of the last data available in the FIFO just
before it empties. When this bit is 1 and FIFO is used, the last available data in the
FIFO is repeatedly sent. This may be useful in PWM mode to avoid duty cycle gaps. If
the FIFO is not used this bit does not have any effect. Default operation is do-not-
repeat.
SBITi defines the state of the output when no transmission takes place. It also defines
the zero polarity for the zero padding in serialiser mode. This bit is padded between
two consecutive transfers as well as tail of the data when PWM_RNGi is larger than bit
depth of data being transferred. this bit is zero by default.
POLAi is used to configure the polarity of the output bit. When set to high the final
output is inverted. Default operation is no inversion.
USEFi bit is used to enable/disable FIFO transfer. When this bit is high data stored in
the FIFO is used for transmission. When it is low, data written to PWM_DATi is
transferred. This bit is 0 as default.
CLRF is used to clear the FIFO. Writing a 1 to this bit clears the FIFO. Writing 0 has no
effect. This is a single shot operation and reading the bit always returns 0.
MSENi is used to determine whether to use PWM algorithm or simple M/S ratio
transmission. When this bit is high M/S transmission is used. This bit is zero as default.
When MODEi is 1, this configuration bit has no effect.
Bit(s)
Field Name
Description
Type
Reset
31:16
Reserved
-
Write as 0, read as don't care
15 MSEN2 Channel 2 M/S Enable
0: PWM algorithm is used
1: M/S transmission is used.
RW 0x0
14
Reserved
-
Write as 0, read as don't care
13 USEF2 Channel 1 Use Fifo
0: Data register is transmitted
1: Fifo is used for transmission
RW 0x0
12 POLA2 Channel 1 Polarity
0 : 0=low 1=high
1: 1=low 0=high
RW 0x0
11 SBIT2 Channel 1 Silence Bit
Defines the state of the output when no
transmission takes place
RW 0x0