Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 137

Reserved

Write as 0, read as don't care

2 FLUSH Flush the RX Buffer into the RX FIFO

This forces the RX Buffer to do an early write.

This is necessary if we have reached the end of

the message and we have bits left in the RX

Buffer. Flushing will write these bits as a single

32 bit word, starting at bit zero. Empty bits will be

packed with zeros. The number of bits written

will be recorded in the FLUSHED Field.

This bit is written as a 1 to initiate a flush. It will

read back as a zero until the flush operation has

completed (as the PCM Clock may be very

slow).

RW 0x0

1 CLR Clear the GRAY Mode Logic

This Bit will reset all the GRAY mode logic, and

flush the RX buffer. It is not self clearing.

RW 0x0

0 EN Enable GRAY Mode

Setting this bit will put the PCM into GRAY

mode. In gray mode the data is received on the

data in and the frame sync pins. The data is

expected to be in data/strobe format.

RW 0x0