Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 135
© 2012 Broadcom Corporation. All rights reserved
6:0 RX RX Request Level
This sets the RX FIFO DREQ level. When the
level is above this the PCM will assert its DMA
DREQ signal to request that some more data is
read out of the RX FIFO.
RW 0x20
INTEN_A Register
Synopsis
Set the reasons for generating an Interrupt. This register cannot be changed whilst the
PCM is running.
Bit(s)
Field Name
Description
Type
Reset
31:4
Reserved
-
Write as 0, read as don't care
3 RXERR RX Error Interrupt
Setting this bit enables interrupts from PCM
block when RX FIFO error occurs.
RW 0x0
2 TXERR TX Error Interrupt
Setting this bit enables interrupts from PCM
block when TX FIFO error occurs.
RW 0x0
1 RXR RX Read Interrupt Enable
Setting this bit enables interrupts from PCM
block when RX FIFO level is greater than or
equal to the specified RXTHR level.
RW 0x0
0 TXW TX Write Interrupt Enable
Setting this bit enables interrupts from PCM
block when TX FIFO level is less than the
specified TXTHR level.
RW 0x0
INTSTC_A Register
Synopsis
This register is used to read and clear the PCM interrupt status. Writing a 1 to the
asserted bit clears the bit. Writing a 0 has no effect.
Bit(s)
Field Name
Description
Type
Reset
31:4
Reserved
-
Write as 0, read as don't care