Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 134
© 2012 Broadcom Corporation. All rights reserved
13:4 CH2POS Channel 2 Position
This sets the bit clock at which the first bit (MS
bit) of channel 2 data occurs in the frame.
0 indicates the first clock of frame.
RW 0x0
3:0 CH2WID Channel 2 Width
This sets the width of channel 2 in bit clocks.
This field has been extended with the CH2WEX
bit giving a total width of (CH2WEX* 16) +
CH2WID + 8. The Maximum supported width is
32 bits.
0 = 8 bits wide
1 = 9 bits wide
RW 0x0
DREQ_A Register
Synopsis
Set the DMA DREQ and Panic thresholds. The PCM drives 2 DMA controls back to the
DMA, one for the TX channel and one for the RX channel. DMA DREQ is used to
request the DMA to perform another transfer, and DMA Panic is used to tell the DMA
to use its panic level of priority when requesting thins on the AXI bus. This register
cannot be changed whilst the PCM is running.
Bit(s)
Field Name
Description
Type
Reset
31
Reserved
-
Write as 0, read as don't care
30:24 TX_PANIC TX Panic Level
This sets the TX FIFO Panic level. When the
level is below this the PCM will assert its TX
DMA Panic signal.
RW 0x10
23
Reserved
-
Write as 0, read as don't care
22:16 RX_PANIC RX Panic Level
This sets the RX FIFO Panic level. When the
level is above this the PCM will assert its RX
DMA Panic signal.
RW 0x30
15
Reserved
-
Write as 0, read as don't care
14:8 TX TX Request Level
This sets the TX FIFO DREQ level. When the
level is below this the PCM will assert its DMA
DREQ signal to request more data is written to
the TX FIFO.
RW 0x30
7
Reserved
-
Write as 0, read as don't care