Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 132
© 2012 Broadcom Corporation. All rights reserved
31 CH1WEX Channel 1 Width Extension Bit
This is the MSB of the channel 1 width
(CH1WID). It allows widths greater than 24 bits
to be programmed and is added here to keep
backwards compatibility with older versions of
the PCM
RW 0x0
30 CH1EN Channel 1 Enable
0 = Channel 1 disabled and no data is received
from channel 1 and written to the RX FIFO.
1 = Channel 1 enabled.
RW 0x0
29:20 CH1POS Channel 1 Position
This sets the bit clock at which the first bit (MS
bit) of channel 1 data occurs in the frame.
0 indicates the first clock of frame.
RW 0x0
19:16 CH1WID Channel 1 Width
This sets the width of channel 1 in bit clocks.
This field has been extended with the CH1WEX
bit giving a total width of (CH1WEX* 16) +
CH1WID + 8. The Maximum supported width is
32 bits.
0 = 8 bits wide
1 = 9 bits wide
RW 0x0
15 CH2WEX Channel 2 Width Extension Bit
This is the MSB of the channel 2 width
(CH2WID). It allows widths greater than 24 bits
to be programmed and is added here to keep
backwards compatibility with older versions of
the PCM
RW 0x0
14 CH2EN Channel 2 Enable
0 = Channel 2 disabled and no data is received
from channel 2 and written to the RX FIFO.
1 = Channel 2 enabled.
RW 0x0
13:4 CH2POS Channel 2 Position
This sets the bit clock at which the first bit (MS
bit) of channel 2 data occurs in the frame.
0 indicates the first clock of frame.
RW 0x0
3:0 CH2WID Channel 2 Width
This sets the width of channel 2 in bit clocks.
This field has been extended with the CH2WEX
bit giving a total width of (CH2WEX* 16) +
CH2WID + 8. The Maximum supported width is
32 bits.
0 = 8 bits wide
1 = 9 bits wide
RW 0x0