Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 13
© 2012 Broadcom Corporation. All rights reserved
AUX_MU_IER_REG Register (0x7E21 5048)
S
YNOPSIS The AUX_MU_IIR_REG register shows the interrupt status.
It also has two FIFO enable status bits and (when writing) FIFO clear bits.
Bit(s) Field Name Description Type Reset
31:8
Reserved, write zero, read as don’t care
7:6 FIFO enables
Both bits always read as 1 as the FIFOs are always
enabled
R 11
5:4 - Always read as zero R 00
3 -
Always read as zero as the mini UART has no
timeout function
R 0
2:1 READ:
Interrupt ID
bits
WRITE:
FIFO clear
bits
On read this register shows the interrupt ID bit
00 : No interrupts
01 : Transmit holding register empty
10 : Receiver holds valid byte
11 : <Not possible>
On write:
Writing with bit 1 set will clear the receive FIFO
Writing with bit 2 set will clear the transmit FIFO
R/W 00
0
Interrupt
pending
This bit is clear whenever an interrupt is pending R 1