Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 128
© 2012 Broadcom Corporation. All rights reserved
9 DMAEN DMA DREQ Enable
0 = Don t generate DMA DREQ requests.
1 = Generates a TX DMA DREQ requests
whenever the TX FIFO level is lower than
TXREQ or generates a RX DMA DREQ when
the RX FIFO level is higher than RXREQ.
RW 0x0
8:7 RXTHR Sets the RX FIFO threshold at which point the
RXR flag is set
00 = set when we have a single sample in the
RX FIFO
01 = set when the RX FIFO is at least full
10 = set when the RX FIFO is at least
11 = set when the RX FIFO is full
RW 0x0
6:5 TXTHR Sets the TX FIFO threshold at which point the
TXW flag is set
00 = set when the TX FIFO is empty
01 = set when the TX FIFO is less than full
10 = set when the TX FIFO is less than full
11 = set when the TX FIFO is full but for one
sample
RW 0x0
4 RXCLR Clear the RX FIFO .
Assert to clear RX FIFO. This bit is self clearing
and is always read as clear
Note that it will take 2 PCM clocks for the FIFO
to be physically cleared.
WO 0x0
3 TXCLR Clear the TX FIFO
Assert to clear TX FIFO. This bit is self clearing
and is always read as clear.
Note that it will take 2 PCM clocks for the FIFO
to be physically cleared.
WO 0x0
2 TXON Enable transmission
0 = Stop transmission. This will stop immediately
if possible or else at the end of the next frame.
The TX FIFO can still be written to to preload
data.
1 = Start transmission. This will start transmitting
at the start of the next frame. Once enabled, the
first data read from the TX FIFO will be placed in
the first channel of the frame, thus ensuring
proper channel synchronisation.
The frame counter will be started whenever
TXON or RXON are set.
This bit can be written whilst the interface is
running.
RW 0x0