Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 12
© 2012 Broadcom Corporation. All rights reserved
AUX_MU_IIR_REG Register (0x7E21 5044)
S
YNOPSIS The AUX_MU_IER_REG register is primary used to enable interrupts
If the DLAB bit in the line control register is set this register gives access to the MS 8 bits
of the baud rate. (Note: there is easier access to the baud rate register)
Bit(s) Field Name Description Type Reset
31:8
Reserved, write zero, read as don’t care
7:0
MS 8 bits
Baudrate
read/write,
DLAB=1
Access to the MS 8 bits of the 16-bit baudrate register.
(Only If bit 7 of the line control register (DLAB bit) is
set)
R/w 0
7:2
Reserved, write zero, read as don’t care
Some of these bits have functions in a 16550
compatible UART but are ignored here
1
Enable receive
interrupt
(DLAB=0)
If this bit is set the interrupt line is asserted whenever
the receive FIFO holds at least 1 byte.
If this bit is clear no receive interrupts are generated.
R 0
0
Enable
transmit
interrupt
(DLAB=0)
If this bit is set the interrupt line is asserted whenever
the transmit FIFO is empty.
If this bit is clear no transmit interrupts are generated.
R 0