Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 118
© 2012 Broadcom Corporation. All rights reserved
Interrupt disable register 2.
Name: IRQ disable 2
Address: 0x220
Reset: 0x000
Bit(s)
R/W
Function
31:0
R/Wbc
Set to disable IRQ source 63:32 (See IRQ table above)
Writing a 1 to a bit will clear the corresponding IRQ enable bit. All other IRQ enable bits are
unaffected.
Base disable register.
Name: IRQ disable 3
Address: 0x224
Reset: 0x000
Bit(s)
R/W
Function
31:8
-
<Unused>
7
R/Wbc
Set to disable Access error type
-
0 IRQ
6
R/Wbc
Set to disable Access error type
-
1 IRQ
5
R/Wbc
Set to disable GPU 1 Halted IRQ
4
R/Wbc
Set to disable GPU 0 Halted IRQ
3
R/Wbc
Set to disable ARM Doorbell 1 IRQ
2
R/Wbc
Set to disable ARM Doorbell 0 IRQ
1
R/Wbc
Set to disable ARM Mailbox IRQ
0
R/Wbc
Set to disable ARM Timer IRQ
Writing a 1 to a bit will clear the corresponding IRQ enable bit. All other IRQ enable bits are
unaffected.