Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 117
© 2012 Broadcom Corporation. All rights reserved
Interrupt enable register 2.
Name: IRQ enable 2
Address: 0x214
Reset: 0x000
Bit(s)
R/W
Function
31:0
R/Wbs
Set to enable IRQ source 63:32 (See IRQ table above)
Writing a 1 to a bit will set the corresponding IRQ enable bit. All other IRQ enable bits are
unaffected. Only bits which are enabled can be seen in the interrupt pending registers. There is no
provision here to see if there are interrupts which are pending but not enabled.
Base Interrupt enable register.
Name: IRQ enable 3
Address: 0x218
Reset: 0x000
Bit(s)
R/W
Function
31:8
R/Wbs
<Unused>
7
R/Wbs
Set to enable Access error type
-
0 IRQ
6
R/Wbs
Set to enable Access error type
-
1 IRQ
5
R/Wbs
Set to enable GPU 1 Halted IRQ
4
R/Wbs
Set to enable GPU 0 Halted IRQ
3
R/Wbs
Set to enable ARM Doorbell 1 IRQ
2
R/Wbs
Set to enable ARM Doorbell 0 IRQ
1
R/Wbs
Set to enable ARM Mailbox IRQ
0
R/Wbs
Set to enable ARM Timer IRQ
Writing a 1 to a bit will set the corresponding IRQ enable bit. All other IRQ enable bits are
unaffected. Again only bits which are enabled can be seen in the basic pending register. There is no
provision here to see if there are interrupts which are pending but not enabled.
Interrupt disable register 1.
Name: IRQ disable 1
Address: 0x21C
Reset: 0x000
Bit(s)
R/W
Function
31:0
R/Wbc
Set to disable IRQ source 31:0 (See IRQ table above)
Writing a 1 to a bit will clear the corresponding IRQ enable bit. All other IRQ enable bits are
unaffected.