Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 116
© 2012 Broadcom Corporation. All rights reserved
Name: FIQ
Address: 0x20C
Reset: 0x000
Bit(s)
R/W
Function
31:8
R
<unused>
7
R
FIQ enable. Set this bit to 1 to enable FIQ generation.
If set to 0 bits 6:0 are don't care.
6:0
R/W
Select FIQ Source
FIQ Source.
The FIQ source values 0-63 correspond to the GPU interrupt table. (See above)
The following values can be used to route ARM specific interrupts to the FIQ vector/routine:
FIQ index
Source
0
-
63
GPU Interrupts (See GPU IRQ table)
64
ARM Timer interrupt
65
ARM Mailbox interrupt
66
ARM Doorbell 0 interrupt
67
ARM Doorbell 1 interrupt
68
GPU0 Halted interrupt (Or GPU1)
69
GPU1 Halted interrupt
70
Illegal access type
-
1 interrupt
71
Illegal access type
-
0 interrupt
72
-
127
Do Not Use
Interrupt enable register 1.
Name: IRQ enable 1
Address: 0x210
Reset: 0x000
Bit(s)
R/W
Function
31:0
R/Wbs
Set to enable IRQ source 31:0 (See IRQ table above)
Writing a 1 to a bit will set the corresponding IRQ enable bit. All other IRQ enable bits are
unaffected. Only bits which are enabled can be seen in the interrupt pending registers. There is no
provision here to see if there are interrupts which are pending but not enabled.