Datasheet
06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 115
© 2012 Broadcom Corporation. All rights reserved
seen on the ARM Peripheral bus. The status of that signal can be read from Error/HALT status
register bit 2.
Illegal access type-1 IRQ (6)
This bit indicates that an address/access error is seen in the ARM control has generated an interrupt.
That can either be an address bit 29..26 was high or when a burst access was seen on the GPU
Peripheral bus. The status of that signal can be read from Error/HALT status register bits 0 and 1.
GPU-1 halted IRQ (5)
This bit indicate that the GPU-1 halted status bit has generated an interrupt. The status of that signal
can be read from Error/HALT status register bits 4.
GPU-0 (or any GPU) halted IRQ (4)
This bit indicate that the GPU-0 halted status bit has generated an interrupt. The status of that signal
can be read from Error/HALT status register bits 3.
In order to allow a fast interrupt (FIQ) routine to cope with GPU 0 OR GPU-1 there is a bit in control
register 1 which, if set will also route a GPU-1 halted status on this bit.
Standard peripheral IRQs (0,1,2,3)
These bits indicate if an interrupt is pending for one of the ARM control peripherals.
GPU pending 1 register.
Name: IRQ pend base
Address: 0x204
Reset: 0x000
Bit(s)
R/W
Function
31:0
R
IRQ pending source 31:0 (See IRQ table above)
This register holds ALL interrupts 0..31 from the GPU side. Some of these interrupts are also
connected to the basic pending register. Any interrupt status bit in here which is NOT connected to
the basic pending will also cause bit 8 of the basic pending register to be set. That is all bits except 7,
9, 10, 18, 19.
GPU pending 2 register.
Name: IRQ pend base
Address: 0x208
Reset: 0x000
Bit(s)
R/W
Function
31:0
R
IRQ pending source 63:32 (See IRQ table above)
This register holds ALL interrupts 32..63 from the GPU side. Some of these interrupts are also
connected to the basic pending register. Any interrupt status bit in here which is NOT connected to
the basic pending will also cause bit 9 of the basic pending register to be set. That is all bits except .
register bits 21..25, 30 (Interrupts 53..57,62).
FIQ register.
The FIQ register control which interrupt source can generate a FIQ to the ARM. Only a single
interrupt can be selected.