Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 114
© 2012 Broadcom Corporation. All rights reserved
Name: IRQ pend base Address: 0x200 Reset: 0x000
19
R
GPU IRQ 57
18
R
GPU IRQ 56
17
R
GPU IRQ 55
16
R
GPU IRQ 54
15
R
GPU IRQ 53
14
R
GPU IRQ 19
13
R
GPU IRQ 18
12
R
GPU IRQ 10
11
R
GPU IRQ 9
10
R
GPU IRQ 7
9
R
One or more bits set in pending register 2
8
R
One or more bits set in pending register 1
7
R
Illegal access type 0 IRQ pending
6
R
Illegal access type 1 IRQ pending
5
R
GPU1 halted IRQ pending
4
R
GPU0 halted IRQ
pending
(Or GPU1 halted if bit 10 of control register 1 is set)
3
R
ARM Doorbell 1 IRQ pending
2
R
ARM Doorbell 0 IRQ pending
1
R
ARM Mailbox IRQ pending
0
R
ARM Timer IRQ pending
GPU IRQ x (10,11..20)
These bits are direct interrupts from the GPU. They have been selected as interrupts which are most
likely to be useful to the ARM. The GPU interrupt selected are 7, 9, 10, 18, 19, 53,54,55,56,57,62. For
details see the GPU interrupts table.
Bits set in pending registers (8,9)
These bits indicates if there are bits set in the pending 1/2 registers. The pending 1/2 registers hold
ALL interrupts 0..63 from the GPU side. Some of these 64 interrupts are also connected to the basic
pending register. Any bit set in pending register 1/2 which is NOT connected to the basic pending
register causes bit 8 or 9 to set. Status bits 8 and 9 should be seen as "There are some interrupts
pending which you don't know about. They are in pending register 1 /2."
Illegal access type-0 IRQ (7)
This bit indicate that the address/access error line from the ARM processor has generated an
interrupt. That signal is asserted when either an address bit 31 or 30 was high or when an access was