Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 113
© 2012 Broadcom Corporation. All rights reserved
ARM peripherals interrupts table.
#
IRQ 0
-
15
#
IRQ 16
-
31
#
IRQ 32
-
47
#
IRQ 48
-
63
0
16
32
48
smi
1
17
33
49
gpio_int[0]
2
18
34
50
gpio_int[1]
3
19
35
51
gpio_int[2]
4
20
36
52
gpio_int[3]
5
21
37
53
i2c_int
6
22
38
54
spi_int
7
23
39
55
pcm_int
8
24
40
56
9
25
41
57
uart_int
10
26
42
58
11
27
43
i2c_spi_slv_int
59
12
28
44
60
13
29
Aux int
45
pwa0
61
14
30
46
pwa1
62
15
31
47
63
The table above has many empty entries. These should not be enabled as they will interfere with the
GPU operation.
ARM peripherals interrupts table.
0
ARM Timer
1
ARM Mailbox
2
ARM Doorbell 0
3
ARM Doorbell 1
4
GPU0 halted (Or GPU1 halted if bit 10 of control register 1 is set)
5
GPU1 halted
6
Illegal access type 1
7
Illegal access type 0
Basic pending register.
The basic pending register shows which interrupt are pending. To speed up interrupts processing, a
number of 'normal' interrupt status bits have been added to this register. This makes the 'IRQ
pending base' register different from the other 'base' interrupt registers
Name: IRQ pend base Address: 0x200 Reset: 0x000
Bit(s) R/W Function
31:21
-
<unused>
20
R
GPU IRQ 62