Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 112
© 2012 Broadcom Corporation. All rights reserved
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7.5 Registers
The base address for the ARM interrupt register is 0x7E00B000.
Registers overview:
Address
offset
7
Name
Notes
0x200
IRQ basic pending
0x204
IRQ pending 1
0x208
IRQ pending 2
0x20C
FIQ control
0x210
Enable IRQs 1
0x214
Enable IRQs 2
0x218
Enable Basic IRQs
0x21C
Disable IRQs 1
0x220
Disable IRQs 2
0x224
Disable Basic IRQs
The following is a table which lists all interrupts which can come from the peripherals which can be
handled by the ARM.
7
This is the offset which needs to be added to the base address to get the full hardware address.