Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 110

7.2 Interrupt pending.

An interrupt vector module has NOT been implemented. To still have adequate interrupt processing

the interrupt pending bits are organized as follows:

ARM IRQs

VC IRQs 0-31

GPU IRQs 32-63

Basic pend.

GPU pend. 0

GPU pend. 1

A few

selected

GPU IRQs

See text

There are three interrupt pending registers.

One basic pending register and two GPU pending registers.

Basic pending register.

The basic pending register has interrupt pending bits for the ARM specific interrupts .

To speed up the interrupt processing it also has a number of selected GPU interrupts which are

deemed most likely to be required in ARM drivers.

Further there are two special GPU pending bits which tell if any of the two other pending registers

has bits set, one bit if a GPU interrupt 0-31 is pending, a second bit if a GPU interrupt 32-63 is

pending. The 'selected GPU interrupts' on the basic pending registers are NOT taken into account for

these two status bits. So the two pending 0,1 status bits tell you that 'there are more interrupt which

you have not seen yet'.

GPU pending registers.

There are two GPU pending registers with one bit per GPU interrupt source.

7.3 Fast Interrupt (FIQ).

The ARM also supports a Fast Interrupt (FIQ). One interrupt sources can be selected to be connected

to the ARM FIQ input. There is also one FIQ enable. An interrupt which is selected as FIQ should have

its normal interrupt enable bit cleared. Otherwise an normal and a FIQ interrupt will be fired at the

same time. Not a good idea!

7.4 Interrupt priority.

There is no priority for any interrupt. If one interrupt is much more important then all others it can

be routed to the FIQ. Any remaining interrupts have to be processed by polling the pending