Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 109
© 2012 Broadcom Corporation. All rights reserved
7 Interrupts
7.1 Introduction
The ARM has two types of interrupt sources:
1. Interrupts coming from the GPU peripherals.
2. Interrupts coming from local ARM control peripherals.
The ARM processor gets three types of interrupts:
1. Interrupts from ARM specific peripherals.
2. Interrupts from GPU peripherals.
3. Special events interrupts.
The ARM specific interrupts are:
• One timer.
• One Mailbox.
• Two Doorbells.
• Two GPU halted interrupts.
• Two Address/access error interrupt
The Mailbox and Doorbell registers are not for general usage.
For each interrupt source (ARM or GPU) there is an interrupt enable bit (read/write) and an interrupt
pending bit (Read Only). All interrupts generated by the arm control block are level sensitive
interrupts. Thus all interrupts remain asserted until disabled or the interrupt source is cleared.
Default the interrupts from doorbell 0,1 and mailbox 0 go to the ARM this means that these
resources should be written by the GPU and read by the ARM. The opposite holds for doorbells 2, 3
and mailbox 1.