Datasheet

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 107
© 2012 Broadcom Corporation. All rights reserved
Register Definitions
Clock Manager General Purpose Clocks Control (CM_GP0CTL, GP1CTL &
GP2CTL)
Address 0x 7e10 1070 CM_GP0CTL
0x 7e10 1078 CM_GP1CTL
0x 7e10 1080 CM_GP2CTL
Bit
Number
Field
Name
Description
Read/
Write
Reset
31-24 PASSWD Clock Manager password “5a” W 0
23-11 - Unused R 0
10-9 MASH
MASH control
0 = integer division
1 = 1-stage MASH (equivalent to non-MASH dividers)
2 = 2-stage MASH
3 = 3-stage MASH
To avoid lock-ups and glitches do not change this
control while BUSY=1 and do not change this control
at the same time as asserting ENAB.
R/W 0
8 FLIP
Invert the clock generator output
This is intended for use in test/debug only. Switching
this control will generate an edge on the clock
generator output. To avoid output glitches do not
switch this control while BUSY=1.
R/W 0
7 BUSY
Clock generator is running
Indicates the clock generator is running. To avoid
glitches and lock-ups, clock sources and setups must
not be changed while this flag is set.
R 0
6 - Unused R 0
5 KILL
Kill the clock generator
0 = no action
1 = stop and reset the clock generator
This is intended for test/debug only. Using this control
may cause a glitch on the clock generator output.
R/W 0
4 ENAB
Enable the clock generator
This requests the clock to start or stop without
glitches. The output clock will not stop immediately
because the cycle must be allowed to complete to
avoid glitches. The BUSY flag will go low when the
final cycle is completed.
R/W 0
3-0 SRC
Clock source
0 = GND
1 = oscillator
2 = testdebug0
3 = testdebug1
4 = PLLA per
5 = PLLC per
6 = PLLD per
7 = HDMI auxiliary
8-15 = GND
To avoid lock-ups and glitches do not change this
control while BUSY=1 and do not change this control
at the same time as asserting ENAB.
R/W 0