Datasheet

PN512 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352 95 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
If the number of WaterLevel bytes (as set in the WaterLevelReg register) or less are
stored in the FIFO buffer, the LoAlert bit is set to logic 1. It is generated according to
Equation 4
:
(4)
13. Interrupt request system
The PN512 indicates certain events by setting the Status1Reg register’s IRq bit and, if
activated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its
interrupt handling capabilities. This allows the implementation of efficient host software.
13.1 Interrupt sources overview
Table 157 shows the available interrupt bits, the corresponding source and the condition
for its activation. The ComIrqReg register’s TimerIRq interrupt bit indicates an interrupt set
by the timer unit which is set when the timer decrements from 1 to 0.
The ComIrqReg register’s TxIRq bit indicates that the transmitter has finished. If the state
changes from sending data to transmitting the end of the frame pattern, the transmitter
unit automatically sets the interrupt bit. The CRC coprocessor sets the DivIrqReg
register’s CRCIRq bit after processing all the FIFO buffer data which is indicated by
CRCReady bit = 1.
The ComIrqReg register’s RxIRq bit indicates an interrupt when the end of the received
data is detected. The ComIrqReg register’s IdleIRq bit is set if a command finishes and
the Command[3:0] value in the CommandReg register changes to idle (see Table 158 on
page 101).
The ComIrqReg register’s HiAlertIRq bit is set to logic 1 when the Status1Reg register’s
HiAlert bit is set to logic 1 which means that the FIFO buffer has reached the level
indicated by the WaterLevel[5:0] bits.
The ComIrqReg register’s LoAlertIRq bit is set to logic 1 when the Status1Reg register’s
LoAlert bit is set to logic 1 which means that the FIFO buffer has reached the level
indicated by the WaterLevel[5:0] bits.
The ComIrqReg register’s ErrIRq bit indicates an error detected by the contactless UART
during send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg.
LoAlert FIFOLength WaterLevel=
Table 157. Interrupt sources
Interrupt flag Interrupt source Trigger action
TimerIRq timer unit the timer counts from 1 to 0
TxIRq transmitter a transmitted data stream ends
CRCIRq CRC coprocessor all data from the FIFO buffer has been processed
RxIRq receiver a received data stream ends
IdleIRq ComIrqReg register command execution finishes
HiAlertIRq FIFO buffer the FIFO buffer is almost full
LoAlertIRq FIFO buffer the FIFO buffer is almost empty
ErrIRq contactless UART an error is detected