Datasheet

Product data sheet

COMPANY PUBLIC

Rev. 5.2 — 16 June 2016

111352 90 of 137

NXP Semiconductors

PN512

Full NFC Forum-compliant frontend

11.6.1 Signal shape for Felica S

C interface support

The FeliCa secure IC is connected to the PN512 via the pins SIGOUT and SIGIN.

The signal at SIGOUT contains the information of the 13.56 MHz clock and the digitized

demodulated signal. The clock and the demodulated signal is combined by using the

logical function exclusive or.

To ensure that this signal is free of spikes, the demodulated signal is digitally filtered first.

The time delay for that digital filtering is in the range of one bit length. The demodulated

signal changes only at a positive edge of the clock.

The register TxSelReg controls the setting at SIGOUT.

The answer of the FeliCa SAM is transferred from SIGIN directly to the antenna driver.

The modulation is done according to the register settings of the antenna drivers.

The clock is switched to AUX1 or AUX2 (see AnalogSelAux).

Note: A HIGH signal on AUX1 and AUX2 has the same level as AVDD. A HIGH signal at

SIGOUT has the same level as SVDD. Alternatively it is possible to use pin D0 as clock

output if a serial interface is used. The HIGH level at D0 is the same as PVDD.

Note: The signal on the antenna is shown in principle only. In reality the waveform is

sinusoidal.

Fig 31. Signal shape for SIGOUT in FeliCa card SAM mode

Fig 32. Signal shape for SIGIN in SAM mode

001aan227

clock

signal on

SIGIN

signal on

antenna

001aan228

clock

demodulated

signal

signal on

SIGOUT