Datasheet

PN512 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352 78 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
9.4.5 7-Bit addressing
During the I
2
C-bus address procedure, the first byte after the START condition is used to
determine which slave will be selected by the master.
Several address numbers are reserved. During device configuration, the designer must
ensure that collisions with these reserved addresses cannot occur. Check the I
2
C-bus
specification for a complete list of reserved addresses.
The I
2
C-bus address specification is dependent on the definition of pin EA. Immediately
after releasing pin NRSTPD or after a power-on reset, the device defines the I
2
C-bus
address according to pin EA.
If pin EA is set LOW, the upper 4 bits of the device bus address are reserved by
NXP Semiconductors and set to 0101b for all PN512 devices. The remaining 3 bits
(ADR_0, ADR_1, ADR_2) of the slave address can be freely configured by the customer
to prevent collisions with other I
2
C-bus devices.
If pin EA is set HIGH, ADR_0 to ADR_5 can be completely specified at the external pins
according to Table 141 on page 69
. ADR_6 is always set to logic 0.
In both modes, the external address coding is latched immediately after releasing the
reset condition. Further changes at the used pins are not taken into consideration.
Depending on the external wiring, the I
2
C-bus address pins can be used for test signal
outputs.
9.4.6 Register write access
To write data from the host controller using the I
2
C-bus to a specific register in the PN512
the following frame format must be used.
• The first byte of a frame indicates the device address according to the I
2
C-bus rules.
• The second byte indicates the register address followed by up to n-data bytes.
In one frame all data bytes are written to the same register address. This enables fast
FIFO buffer access. The Read/Write (R/W
) bit is set to logic 0.
Fig 22. First byte following the START procedure
001aak591 slave address
bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
MSB LSB