Datasheet

Product data sheet

COMPANY PUBLIC

Rev. 5.2 — 16 June 2016

111352 70 of 137

NXP Semiconductors

PN512

Full NFC Forum-compliant frontend

9.2 Serial Peripheral Interface

A serial peripheral interface (SPI compatible) is supported to enable high-speed

communication to the host. The interface can handle data speeds up to 10 Mbit/s. When

communicating with a host, the PN512 acts as a slave, receiving data from the external

host for register settings, sending and receiving data relevant for RF interface

communication.

An interface compatible with SPI enables high-speed serial communication between the

PN512 and a microcontroller. The implemented interface is in accordance with the SPI

standard.

The timing specification is given in Section 25.1 on page 117

The PN512 acts as a slave during SPI communication. The SPI clock signal SCK must be

generated by the master. Data communication from the master to the slave uses the

MOSI line. The MISO line is used to send data from the PN512 to the master.

Data bytes on both MOSI and MISO lines are sent with the MSB first. Data on both MOSI

and MISO lines must be stable on the rising edge of the clock and can be changed on the

falling edge. Data is provided by the PN512 on the falling clock edge and is stable during

the rising clock edge.

9.2.1 SPI read data

Reading data using SPI requires the byte order shown in Table 143 to be used. It is

possible to read out up to n-data bytes.

The first byte sent defines both the mode and the address.

[1] X = Do not care.

Remark: The MSB must be sent first.

9.2.2 SPI write data

To write data to the PN512 using SPI requires the byte order shown in Table 144. It is

possible to write up to n data bytes by only sending one address byte.

Fig 13. SPI connection to host

001aan220

PN512

SCK

MOSI

MISO

NSS

Table 143. MOSI and MISO byte order

Line Byte 0 Byte 1 Byte 2 To Byte n Byte n + 1

MOSI address 0 address 1 address 2 ... address n 00

MISO X

[1]

data 0 data 1 ... data n  1data n