Datasheet

PN512 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352 69 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
[1] only available in HVQFN 40.
Table 141. Connection protocol for detecting different interface types
Pin Interface type
UART (input) SPI (output) I
2
C-bus (I/O)
SDA RX NSS SDA
I
2
C001
EA01EA
D7 TX MISO SCL
D6 MX MOSI ADR_0
D5 DTRQ SCK ADR_1
D4 - - ADR_2
D3 - - ADR_3
D2 - - ADR_4
D1 - - ADR_5
Table 142. Connection scheme for detecting the different interface types
PN512 Parallel Interface Type Serial Interface Types
Separated Read/Write Strobe Common Read/Write Strobe
Pin Dedicated
Address Bus
Multiplexed
Address Bus
Dedicated
Address Bus
Multiplexed
Address Bus
UART SPI
I
2
C
ALE 1 ALE 1 AS RX NSS SDA
A5
[1]
A5 0 A5 0 000
A4
[1]
A4 0 A4 0 000
A3
[1]
A3 0 A3 0 000
A2
[1]
A2 1 A2 1 000
A1A1 1 A1 1 001
A0A0 1 A0 0 01EA
NRD
[1]
NRD NRD NDS NDS 1 1 1
NWR
[1]
NWR NWR RD/NWR RD/NWR 1 1 1
NCS
[1]
NCS NCS NCS NCS NCS NCS NCS
D7
D7 D7 D7 D7 TX MISO SCL
D6
D6 D6 D6 D6 MX MOSI ADR_0
D5
D5 AD5 D5 AD5 DTRQ SCK ADR_1
D4
D4 AD4 D4 AD4 --ADR_2
D3
D3 AD3 D3 AD3 --ADR_3
D2
D2 AD2 D2 AD2 --ADR_4
D1
D1 AD1 D1 AD1 --ADR_5
D0
D0 AD0 D0 AD0 --ADR_6
Remark: Overview on the pin behavior
Pin behavior Input
Output In/Out