Datasheet

PN512 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352 68 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
8.2.4.13 RFTReg
9. Digital interfaces
9.1 Automatic microcontroller interface detection
The PN512 supports direct interfacing of hosts using SPI, I
2
C-bus or serial UART
interfaces. The PN512 resets its interface and checks the current host interface type
automatically after performing a power-on or hard reset. The PN512 identifies the host
interface by sensing the logic levels on the control pins after the reset phase. This is done
using a combination of fixed pin connections. Table 141
shows the different connection
configurations.
Table 135. RFTReg register (address 3Ch); reset value: FFh, 11111111b
7 6 5 4 3 2 1 0
11111111
Access
Rights
RFT RFT RFT RFT RFT RFT RFT RFT
Table 136. Description of RFTReg bits
Bit Symbol Description
7 to 0 - Reserved for production tests.
Table 137. RFTReg register (address 3Dh, 3Fh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
00000000
Access
Rights
RFT RFT RFT RFT RFT RFT RFT RFT
Table 138. Description of RFTReg bits
Bit Symbol Description
7 to 0 - Reserved for production tests.
Table 139. RFTReg register (address 3Eh); reset value: 03h, 00000011b
7 6 5 4 3 2 1 0
00000011
Access
Rights
RFT RFT RFT RFT RFT RFT RFT RFT
Table 140. Description of RFTReg bits
Bit Symbol Description
7 to 0 - Reserved for production tests.