Datasheet

Product data sheet

COMPANY PUBLIC

Rev. 5.2 — 16 June 2016

111352 63 of 137

NXP Semiconductors

PN512

Full NFC Forum-compliant frontend

8.2.4.4 TestPinEnReg

Enables the pin output driver on the 8-bit parallel bus.

8.2.4.5 TestPinValueReg

Defines the values for the 7-bit parallel port when it is used as I/O.

Table 117. TestPinEnReg register (address 33h); reset value: 80h, 10000000b

7 6 5 4 3 2 1 0

RS232LineEn TestPinEn

Access

Rights

r/w r/w r/w r/w r/w r/w r/w r/w

Table 118. Description of TestPinEnReg bits

Bit Symbol Description

7 RS232LineEn Set to logic 0, the lines MX and DTRQ for the serial UART are

disabled.

6 to 0 TestPinEn Enables the pin output driver on the 8-bit parallel interface.

Example:

Setting bit 0 to 1 enables D0

Setting bit 5 to 1 enables D5

Note: Only valid if one of serial interfaces is used.

If the SPI interface is used only D0 to D4 can be used. If the serial

UART interface is used and RS232LineEn is set to logic 1 only D0 to

D4 can be used.

Table 119. TestPinValueReg register (address 34h); reset value: 00h, 00000000b

7 6 5 4 3 2 1 0

UseIO TestPinValue

Access

Rights

r/w r/w r/w r/w r/w r/w r/w r/w

Table 120. Description of TestPinValueReg bits

Bit Symbol Description

7 UseIO Set to logic 1, this bit enables the I/O functionality for the 7-bit parallel

port in case one of the serial interfaces is used. The input/output

behavior is defined by TestPinEn in register TestPinEnReg. The value

for the output behavior is defined in the bits TestPinVal.

Note: If SAMClkD1 is set to logic 1, D1 can not be used as I/O.

6 to 0 TestPinValue Defines the value of the 7-bit parallel port, when it is used as I/O. Each

output has to be enabled by the TestPinEn bits in register

TestPinEnReg.

Note: Reading the register indicates the actual status of the pins D6 -

D0 if UseIO is set to logic 1. If UseIO is set to logic 0, the value of the