Datasheet

Product data sheet

COMPANY PUBLIC

Rev. 5.2 — 16 June 2016

111352 48 of 137

NXP Semiconductors

PN512

Full NFC Forum-compliant frontend

8.2.2.13 MifNFCReg

Defines ISO/IEC 14443A/MIFARE/NFC specific settings in target or Card Operating

mode.

Table 71. MifNFCReg register (address 1Ch); reset value: 62h, 01100010b

7 6 5 4 3 2 1 0

SensMiller TauMiller MFHalted TxWait

Access

Rights

r/w r/w r/w r/w r/w r/w r/w r/w

Table 72. Description of MifNFCReg bits

Bit Symbol Description

7 to 5 SensMiller These bits define the sensitivity of the Miller decoder.

4 to 3 TauMiller These bits define the time constant of the Miller decoder.

2 MFHalted Set to logic 1, this bit indicates that the PN512 is set to HALT mode in

Card Operation mode at 106 kbit. This bit is either set by the host

controller or by the internal state machine and indicates that only the

code 52h is accepted as a request command. This bit is cleared

automatically by a RF reset.

1 to 0 TxWait These bits define the minimum response time between receive and

transmit in number of data bits + 7 data bits.

The shortest possible minimum response time is 7 data bits.

(TxWait=0). The minimum response time can be increased by the

number of bits defined in TxWait. The longest minimum response time

is 10 data bits (TxWait = 3).

If a transmission of a frame is started before the minimum response

time is over, the PN512 waits before transmitting the data until the

minimum response time is over.

If a transmission of a frame is started after the minimum response time

is over, the frame is started immediately if the data bit synchronization

is correct. (adjustable with TxBitPhase).