Datasheet

PN512 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352 45 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
8.2.2.10 DemodReg
Defines demodulator settings.
Table 65. DemodReg register (address 19h); reset value: 4Dh, 01001101b
7 6 5 4 3 2 1 0
AddIQ FixIQ TPrescal
Even
TauRcv TauSync
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 66. Description of DemodReg bits
Bit Symbol Description
7 to 6 AddIQ Defines the use of I and Q channel during reception
Note: FixIQ has to be set to logic 0 to
enable the following settings.
Value Description
00 Select the stronger channel
01 Select the stronger and freeze the selected during communication
10 combines the I and Q channel
11 Reserved
5 FixIQ If set to logic 1 and the bits of AddIQ are set to X0, the reception is fixed to
I channel.
If set to logic 1 and the bits of AddIQ are set to X1, the reception is fixed to
Q channel.
NOTE: If SIGIN/SIGOUT is used as S2C interface FixIQ set to 1 and AddIQ
set to X0 is rewired.
4 TPrescalE
ven
If set to logic 0 the following formula is used to calculate fTimer of the
prescaler:
f
Timer
= 13.56 MHz / (2 * TPreScaler + 1).
If set to logic 1 the following formula is used to calculate fTimer of the
prescaler:
fTimer = 13.56 MHz / (2 * TPreScaler + 2).
(Default TPrescalEven is logic 0)
The behaviour for the version 1.0 is described in Section 20 “
Errata
sheet” on page 109.
3 to 2 TauRcv Changes the time constant of the internal during data reception.
Note: If set to 00, the PLL is frozen during data reception.
1 to 0 TauSync Changes the time constant of the internal PLL during burst.