Datasheet

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Product data sheet

COMPANY PUBLIC

Rev. 5.2 — 16 June 2016

111352 39 of 137

NXP Semiconductors

PN512

Full NFC Forum-compliant frontend

8.2.2.4 RxModeReg

Defines the data rate and framing during reception.

Table 53. RxModeReg register (address 13h); reset value: 00h, 00000000b

7 6 5 4 3 2 1 0

RxCRCEn RxSpeed RxNoErr RxMultiple RxFraming

Access

Rights

r/w dy dy dy r/w r/w dy dy

Table 54. Description of RxModeReg bits

Bit Symbol Description

7 RxCRCEn Set to logic 1, this bit enables the CRC calculation during reception.

Note: This bit shall only be set to logic 0 at 106 kbit.

6 to 4 RxSpeed Defines the bit rate while data transmission.

The PN512’s analog part handles only transfer speeds up to 424 kbit

internally, the digital UART handles the higher transfer speeds as well.

Value Description

000 106 kbit

001 212 kbit

010 424 kbit

011 848 kbit

100 1696 kbit

101 3392 kbit

110 Reserved

111 Reserved

Note: The bit coding for transfer speeds above 424 kbit is equivalent to

the bit coding of Active Communication mode 424 kbit (Ecma 340).

3 RxNoErr If set to logic 1 a not valid received data stream (less than 4 bits

received) will be ignored. The receiver will remain active.

For ISO/IEC14443B also RxSOFReq logic 1 is required to ignore a non

valid datastream.

2 RxMultiple Set to logic 0, the receiver is deactivated after receiving a data frame.

Set to logic 1, it is possible to receive more than one data frame. Having

set this bit, the receive and transceive commands will not terminate

automatically. In this case the multiple receiving can only be deactivated

by writing any command (except the Receive command) to the

CommandReg register or by clearing the bit by the host controller.

At the end of a received data stream an error byte is added to the FIFO.

The error byte is a copy of the ErrorReg register.

The behaviour for version 1.0 is described in Section 20 “

Errata sheet”

on page 109.