Datasheet

PN512 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352 38 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
8.2.2.3 TxModeReg
Defines the data rate and framing during transmission.
Table 51. TxModeReg register (address 12h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TxCRCEn TxSpeed InvMod TxMix TxFraming
Access
Rights
r/w dydydyr/wr/wdydy
Table 52. Description of TxModeReg bits
Bit Symbol Description
7 TxCRCEn Set to logic 1, this bit enables the CRC generation during data
transmission.
Note: This bit shall only be set to logic 0 at 106 kbit.
6 to 4 TxSpeed Defines the bit rate while data transmission.
Value Description
000 106 kbit
001 212 kbit
010 424 kbit
011 848 kbit
100 1696 kbit
101 3392 kbit
110 Reserved
111 Reserved
Note: The bit coding for transfer speeds above 424 kbit is equivalent to
the bit coding of Active Communication mode 424 kbit (Ecma 340).
3 InvMod Set to logic 1, the modulation for transmitting data is inverted.
2 TxMix Set to logic 1, the signal at pin SIGIN is mixed with the internal coder
(see Section 11.6 “
S
2
C interface support”).
1 to 0 TxFraming Defines the framing used for data transmission.
Value Description
00 ISO/IEC 14443A/MIFARE and Passive Communication mode
106 kbit
01 Active Communication mode
10 FeliCa and Passive communication mode 212 and 424 kbit
11 ISO/IEC 14443B