Datasheet

PN512 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352 33 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
8.2.1.12 WaterLevelReg
Defines the level for FIFO under- and overflow warning.
8.2.1.13 ControlReg
Miscellaneous control bits.
Table 39. WaterLevelReg register (address 0Bh); reset value: 08h, 00001000b
7 6 5 4 3 2 1 0
0 0 WaterLevel
Access
Rights
RFU RFU r/w r/w r/w r/w r/w r/w
Table 40. Description of WaterLevelReg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 to 0 WaterLevel This register defines a warning level to indicate a FIFO-buffer over- or
underflow:
The bit HiAlert in Status1Reg is set to logic 1, if the remaining number
of bytes in the FIFO-buffer space is equal or less than the defined
number of WaterLevel bytes.
The bit LoAlert in Status1Reg is set to logic 1, if equal or less than
WaterLevel bytes are in the FIFO.
Note: For the calculation of HiAlert and LoAlert see Table 31
Table 41. ControlReg register (address 0Ch); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TStopNow TStartNow WrNFCIDtoFIFO Initiator 0 RxLastBits
Access
Rights
w w dy r/wRFUrrr
Table 42. Description of ControlReg bits
Bit Symbol Description
7 TStopNow Set to logic 1, the timer stops immediately.
Reading this bit will always return 0.
6 TStartNow Set to logic 1 starts the timer immediately.
Reading this bit will always return 0.
5 WrNFCIDtoFIFO Set to logic 1, the internal stored NFCID (10 bytes) is copied into the
FIFO.
Afterwards the bit is cleared automatically
4 Initiator Set to logic 1, the PN512 acts as initiator, otherwise it acts as target
3 - Reserved for future use.
2 to 0 RxLastBits Shows the number of valid bits in the last received byte. If zero, the
whole byte is valid.