Datasheet

PN512 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352 32 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
8.2.1.10 FIFODataReg
In- and output of 64 byte FIFO-buffer.
8.2.1.11 FIFOLevelReg
Indicates the number of bytes stored in the FIFO.
Table 35. FIFODataReg register (address 09h); reset value: XXh, XXXXXXXXb
7 6 5 4 3 2 1 0
FIFOData
Access
Rights
dy dy dy dy dy dy dy dy
Table 36. Description of FIFODataReg bits
Bit Symbol Description
7 to 0 FIFOData Data input and output port for the internal 64 byte FIFO-buffer. The
FIFO-buffer acts as parallel in/parallel out converter for all serial data
stream in- and outputs.
Table 37. FIFOLevelReg register (address 0Ah); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
FlushBuffer FIFOLevel
Access
Rights
w rrrrrrr
Table 38. Description of FIFOLevelReg bits
Bit Symbol Description
7 FlushBuffer Set to logic 1, this bit clears the internal FIFO-buffer’s read- and
write-pointer and the bit BufferOvfl in the register ErrReg immediately.
Reading this bit will always return 0.
6 to 0 FIFOLevel Indicates the number of bytes stored in the FIFO-buffer. Writing to the
FIFODataReg increments, reading decrements the FIFOLevel.