Datasheet

PN512 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352 26 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
8.2.1.4 DivIEnReg
Control bits to enable and disable the passing of interrupt requests.
Table 23. DivIEnReg register (address 03h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
IRQPushPull 0 0 SiginActIEn ModeIEn CRCIEn RFOnIEn RFOffIEn
Access
Rights
r/w RFU RFU r/w r/w r/w r/w r/w
Table 24. Description of DivIEnReg bits
Bit Symbol Description
7 IRQPushPull Set to logic 1, the pin IRQ works as standard CMOS output pad.
Set to logic 0, the pin IRQ works as open drain output pad.
6 to 5 - Reserved for future use.
4 SiginActIEn Allows the SIGIN active interrupt request to be propagated to pin IRQ.
3 ModeIEn Allows the mode interrupt request (indicated by bit ModeIRq) to be
propagated to pin IRQ.
2 CRCIEn Allows the CRC interrupt request (indicated by bit CRCIRq) to be
propagated to pin IRQ.
1 RfOnIEn Allows the RF field on interrupt request (indicated by bit RfOnIRq) to
be propagated to pin IRQ.
0 RfOffIEn Allows the RF field off interrupt request (indicated by bit RfOffIRq) to
be propagated to pin IRQ.