Datasheet

PN512 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352 25 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
8.2.1.3 CommIEnReg
Control bits to enable and disable the passing of interrupt requests.
Table 21. CommIEnReg register (address 02h); reset value: 80h, 10000000b
7 6 5 4 3 2 1 0
IRqInv TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn ErrIEn TimerIEn
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 22. Description of CommIEnReg bits
Bit Symbol Description
7 IRqInv Set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq in the
register Status1Reg. Set to logic 0, the signal on pin IRQ is equal to bit IRq.
In combination with bit IRqPushPull in register DivIEnReg, the default value
of 1 ensures, that the output level on pin IRQ is 3-state.
6 TxIEn Allows the transmitter interrupt request (indicated by bit TxIRq) to be
propagated to pin IRQ.
5 RxIEn Allows the receiver interrupt request (indicated by bit RxIRq) to be
propagated to pin IRQ.
4 IdleIEn Allows the idle interrupt request (indicated by bit IdleIRq) to be propagated to
pin IRQ.
3 HiAlertIEn Allows the high alert interrupt request (indicated by bit HiAlertIRq) to be
propagated to pin IRQ.
2 LoAlertIEn Allows the low alert interrupt request (indicated by bit LoAlertIRq) to be
propagated to pin IRQ.
1 ErrIEn Allows the error interrupt request (indicated by bit ErrIRq) to be propagated
to pin IRQ.
0 TimerIEn Allows the timer interrupt request (indicated by bit TimerIRq) to be
propagated to pin IRQ.