Datasheet

PN512 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352 22 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
6 TxSelReg Selects the internal sources for the antenna driver
7 RxSelReg Selects internal receiver settings
8 RxThresholdReg Selects thresholds for the bit decoder
9 DemodReg Defines demodulator settings
A FelNFC1Reg Defines the length of the valid range for the receive package
B FelNFC2Reg Defines the length of the valid range for the receive package
C MifNFCReg Controls the communication in ISO/IEC 14443/MIFARE and NFC
target mode at 106 kbit
D ManualRCVReg Allows manual fine tuning of the internal receiver
E TypeBReg Configure the ISO/IEC 14443 type B
F SerialSpeedReg Selects the speed of the serial UART interface
Page 2: CFG
0 PageReg Selects the register page
1 CRCResultReg Shows the actual MSB and LSB values of the CRC calculation
2
3 GsNOffReg Selects the conductance of the antenna driver pins TX1 and TX2 for
modulation, when the driver is switched off
4 ModWidthReg Controls the setting of the ModWidth
5 TxBitPhaseReg Adjust the TX bit phase at 106 kbit
6 RFCfgReg Configures the receiver gain and RF level
7 GsNOnReg Selects the conductance of the antenna driver pins TX1 and TX2 for
modulation when the drivers are switched on
8 CWGsPReg Selects the conductance of the antenna driver pins TX1 and TX2 for
modulation during times of no modulation
9 ModGsPReg Selects the conductance of the antenna driver pins TX1 and TX2 for
modulation during modulation
A TModeReg
TPrescalerReg
Defines settings for the internal timer
B
C TReloadReg Describes the 16-bit timer reload value
D
E TCounterValReg Shows the 16-bit actual timer value
F
Page 3: TestRegister
0 PageReg selects the register page
1 TestSel1Reg General test signal configuration
2 TestSel2Reg General test signal configuration and PRBS control
3 TestPinEnReg Enables pin output driver on 8-bit parallel bus (Note: For serial
interfaces only)
4TestPin
ValueReg
Defines the values for the 8-bit parallel bus when it is used as I/O bus
5 TestBusReg Shows the status of the internal testbus
6 AutoTestReg Controls the digital selftest
Table 15. PN512 registers overview
…continued
Addr
(hex)
Register Name Function