Datasheet

PN512 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352 132 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
Table 78. Description of SerialSpeedReg bits . . . . . . . . .51
Table 79. PageReg register (address 20h); reset value: 00h,
00000000b . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 80. Description of PageReg bits . . . . . . . . . . . . . . .52
Table 81. CRCResultReg register (address 21h); reset
value: FFh, 11111111b. . . . . . . . . . . . . . . . . . . .52
Table 82. Description of CRCResultReg bits . . . . . . . . . .52
Table 83. CRCResultReg register (address 22h); reset
value: FFh, 11111111b. . . . . . . . . . . . . . . . . . . .52
Table 84. Description of CRCResultReg bits . . . . . . . . . .53
Table 85. GsNOffReg register (address 23h); reset value:
88h, 10001000b . . . . . . . . . . . . . . . . . . . . . . . .53
Table 86. Description of GsNOffReg bits . . . . . . . . . . . . .53
Table 87. ModWidthReg register (address 24h); reset value:
26h, 00100110b . . . . . . . . . . . . . . . . . . . . . . . .54
Table 88. Description of ModWidthReg bits . . . . . . . . . . .54
Table 89. TxBitPhaseReg register (address 25h); reset
value: 87h, 10000111b . . . . . . . . . . . . . . . . . . .54
Table 90. Description of TxBitPhaseReg bits . . . . . . . . . .54
Table 91. RFCfgReg register (address 26h); reset value:
48h, 01001000b . . . . . . . . . . . . . . . . . . . . . . . .55
Table 92. Description of RFCfgReg bits . . . . . . . . . . . . .55
Table 93. GsNOnReg register (address 27h); reset value:
88h, 10001000b . . . . . . . . . . . . . . . . . . . . . . . .56
Table 94. Description of GsNOnReg bits . . . . . . . . . . . . .56
Table 95. CWGsPReg register (address 28h); reset value:
20h, 00100000b . . . . . . . . . . . . . . . . . . . . . . . .56
Table 96. Description of CWGsPReg bits. . . . . . . . . . . . .56
Table 97. ModGsPReg register (address 29h); reset value:
20h, 00100000b . . . . . . . . . . . . . . . . . . . . . . . .57
Table 98. Description of ModGsPReg bits . . . . . . . . . . . .57
Table 99. TModeReg register (address 2Ah); reset value:
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .57
Table 100. Description of TModeReg bits . . . . . . . . . . . . .57
Table 101. TPrescalerReg register (address 2Bh); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .58
Table 102. Description of TPrescalerReg bits . . . . . . . . . .58
Table 103. TReloadReg (Higher bits) register (address 2Ch);
reset value: 00h, 00000000b . . . . . . . . . . . . . .59
Table 104. Description of the higher TReloadReg bits . . .59
Table 105. TReloadReg (Lower bits) register (address 2Dh);
reset value: 00h, 00000000b . . . . . . . . . . . . . .59
Table 106. Description of lower TReloadReg bits . . . . . . .59
Table 107. TCounterValReg (Higher bits) register (address
2Eh); reset value: XXh, XXXXXXXXb . . . . . . .60
Table 108. Description of the higher TCounterValReg bits 60
Table 109. TCounterValReg (Lower bits) register (address
2Fh); reset value: XXh, XXXXXXXXb. . . . . . . .60
Table 110. Description of lower TCounterValReg bits . . . .60
Table 111. PageReg register (address 30h); reset value: 00h,
00000000b . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 112. Description of PageReg bits. . . . . . . . . . . . . . .61
Table 113. TestSel1Reg register (address 31h); reset value:
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .62
Table 114. Description of TestSel1Reg bits . . . . . . . . . . . .62
Table 115. TestSel2Reg register (address 32h); reset value:
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .62
Table 116. Description of TestSel2Reg bits . . . . . . . . . . . .62
Table 117. TestPinEnReg register (address 33h); reset
value: 80h, 10000000b . . . . . . . . . . . . . . . . . . 63
Table 118. Description of TestPinEnReg bits . . . . . . . . . . 63
Table 119. TestPinValueReg register (address 34h); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 63
Table 120. Description of TestPinValueReg bits . . . . . . . . 63
Table 121. TestBusReg register (address 35h); reset value:
XXh, XXXXXXXXb. . . . . . . . . . . . . . . . . . . . . . 64
Table 122. Description of TestBusReg bits . . . . . . . . . . . . 64
Table 123. AutoTestReg register (address 36h); reset value:
40h, 01000000b. . . . . . . . . . . . . . . . . . . . . . . . 64
Table 124. Description of bits . . . . . . . . . . . . . . . . . . . . . . 64
Table 125. VersionReg register (address 37h); reset value:
XXh, XXXXXXXXb. . . . . . . . . . . . . . . . . . . . . . 65
Table 126. Description of VersionReg bits . . . . . . . . . . . . 65
Table 127. AnalogTestReg register (address 38h); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 66
Table 128. Description of AnalogTestReg bits . . . . . . . . . 66
Table 129. TestDAC1Reg register (address 39h); reset
value: XXh, 00XXXXXXb . . . . . . . . . . . . . . . . . 67
Table 130. Description of TestDAC1Reg bits . . . . . . . . . . 67
Table 131. TestDAC2Reg register (address 3Ah); reset
value: XXh, 00XXXXXXb . . . . . . . . . . . . . . . . . 67
Table 132. Description ofTestDAC2Reg bits. . . . . . . . . . . 67
Table 133. TestADCReg register (address 3Bh); reset value:
XXh, XXXXXXXXb. . . . . . . . . . . . . . . . . . . . . . 67
Table 134. Description of TestADCReg bits . . . . . . . . . . . 67
Table 135. RFTReg register (address 3Ch); reset value:
FFh, 11111111b . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 136. Description of RFTReg bits. . . . . . . . . . . . . . . 68
Table 137. RFTReg register (address 3Dh, 3Fh); reset value:
00h, 00000000b. . . . . . . . . . . . . . . . . . . . . . . . 68
Table 138. Description of RFTReg bits. . . . . . . . . . . . . . . 68
Table 139. RFTReg register (address 3Eh); reset value:
03h, 00000011b . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 140. Description of RFTReg bits. . . . . . . . . . . . . . . 68
Table 141. Connection protocol for detecting different
interface types . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 142. Connection scheme for detecting the different
interface types . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 143. MOSI and MISO byte order . . . . . . . . . . . . . . 70
Table 144. MOSI and MISO byte order . . . . . . . . . . . . . . 71
Table 145. Address byte 0 register; address MOSI . . . . . 71
Table 146. BR_T0 and BR_T1 settings . . . . . . . . . . . . . . 72
Table 147. Selectable UART transfer speeds . . . . . . . . . 72
Table 148. UART framing . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 149. Read data byte order . . . . . . . . . . . . . . . . . . . 73
Table 150. Write data byte order . . . . . . . . . . . . . . . . . . . 73
Table 151. Address byte 0 register; address MOSI . . . . . 75
Table 152. Supported interface types . . . . . . . . . . . . . . . . 82
T
a
ble 153. Register and bit settings controlling the signal on
pin TX1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 154. Register and bit settings controlling the signal on
pin TX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 155. Setting of the bits RFlevel in register RFCfgReg
(RFLevel amplifier deactivated) . . . . . . . . . . . . 86
Table 156. CRC coprocessor parameters . . . . . . . . . . . . 93
Table 157. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . 95