Datasheet

PN512 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352 131 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
34. Tables
Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .4
Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .5
Table 3. Pin description HVQFN32 . . . . . . . . . . . . . . . .10
Table 4. Pin description HVQFN40 . . . . . . . . . . . . . . . .11
Table 5. Pin description TFBGA64. . . . . . . . . . . . . . . . .12
Table 6. Communication overview for
ISO/IEC 14443 A/MIFARE reader/writer . . . . .14
Table 7. Communication overview for FeliCa
reader/writer . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 8. FeliCa framing and coding . . . . . . . . . . . . . . . .16
Table 9. Start value for the CRC Polynomial: (00h), (00h)16
Table 10. Communication overview for Active
communication mode . . . . . . . . . . . . . . . . . . . .18
Table 11. Communication overview for Passive
communication mode . . . . . . . . . . . . . . . . . . . .19
Table 12. Framing and coding overview. . . . . . . . . . . . . .20
Table 13. MIFARE Card operation mode . . . . . . . . . . . . .20
Table 14. FeliCa Card operation mode . . . . . . . . . . . . . .21
Table 15. PN512 registers overview . . . . . . . . . . . . . . . .21
Table 16. Behavior of register bits and its designation. . .23
Table 17. PageReg register (address 00h); reset value: 00h,
0000000b . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 18. Description of PageReg bits . . . . . . . . . . . . . . .24
Table 19. CommandReg register (address 01h); reset
value: 20h, 00100000b . . . . . . . . . . . . . . . . . . .24
Table 20. Description of CommandReg bits. . . . . . . . . . .24
Table 21. CommIEnReg register (address 02h); reset value:
80h, 10000000b . . . . . . . . . . . . . . . . . . . . . . . .25
Table 22. Description of CommIEnReg bits . . . . . . . . . . .25
Table 23. DivIEnReg register (address 03h); reset value:
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .26
Table 24. Description of DivIEnReg bits. . . . . . . . . . . . . .26
Table 25. CommIRqReg register (address 04h); reset value:
14h, 00010100b . . . . . . . . . . . . . . . . . . . . . . . .27
Table 26. Description of CommIRqReg bits . . . . . . . . . . .27
Table 27. DivIRqReg register (address 05h); reset value:
XXh, 000X00XXb . . . . . . . . . . . . . . . . . . . . . . .28
Table 28. Description of DivIRqReg bits . . . . . . . . . . . . .28
Table 29. ErrorReg register (address 06h); reset value: 00h,
00000000b . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 30. Description of ErrorReg bits . . . . . . . . . . . . . . .29
Table 31. Status1Reg register (address 07h); reset value:
XXh, X100X01Xb . . . . . . . . . . . . . . . . . . . . . . .30
Table 32. Description of Status1Reg bits . . . . . . . . . . . . .30
Table 33. Status2Reg register (address 08h); reset value:
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .31
Table 34. Description of Status2Reg bits . . . . . . . . . . . . .31
Table 35. FIFODataReg register (address 09h); reset value:
XXh, XXXXXXXXb . . . . . . . . . . . . . . . . . . . . . .32
Table 36. Description of FIFODataReg bits . . . . . . . . . . .32
Table 37. FIFOLevelReg register (address 0Ah); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .32
Table 38. Description of FIFOLevelReg bits. . . . . . . . . . .32
Table 39. WaterLevelReg register (address 0Bh); reset
value: 08h, 00001000b . . . . . . . . . . . . . . . . . . .33
Table 40. Description of WaterLevelReg bits . . . . . . . . . .33
Table 41. ControlReg register (address 0Ch); reset value:
00h, 00000000b. . . . . . . . . . . . . . . . . . . . . . . . 33
Table 42. Description of ControlReg bits . . . . . . . . . . . . 33
Table 43. BitFramingReg register (address 0Dh); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 34
Table 44. Description of BitFramingReg bits . . . . . . . . . . 34
Table 45. CollReg register (address 0Eh); reset value:
XXh, 101XXXXXb . . . . . . . . . . . . . . . . . . . . . . 35
Table 46. Description of CollReg bits. . . . . . . . . . . . . . . . 35
Table 47. PageReg register (address 10h); reset value: 00h,
00000000b. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 48. Description of PageReg bits . . . . . . . . . . . . . . 36
Table 49. ModeReg register (address 11h); reset value:
3Bh, 00111011b . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 50. Description of ModeReg bits . . . . . . . . . . . . . . 37
Table 51. TxModeReg register (address 12h); reset value:
00h, 00000000b. . . . . . . . . . . . . . . . . . . . . . . . 38
Table 52. Description of TxModeReg bits . . . . . . . . . . . . 38
Table 53. RxModeReg register (address 13h); reset value:
00h, 00000000b. . . . . . . . . . . . . . . . . . . . . . . . 39
Table 54. Description of RxModeReg bits . . . . . . . . . . . . 39
Table 55. TxControlReg register (address 14h); reset value:
80h, 10000000b. . . . . . . . . . . . . . . . . . . . . . . . 40
Table 56. Description of TxControlReg bits . . . . . . . . . . . 40
Table 57. TxAutoReg register (address 15h); reset value:
00h, 00000000b. . . . . . . . . . . . . . . . . . . . . . . . 41
Table 58. Description of TxAutoReg bits . . . . . . . . . . . . . 41
Table 59. TxSelReg register (address 16h); reset value:
10h, 00010000b. . . . . . . . . . . . . . . . . . . . . . . . 42
Table 60. Description of TxSelReg bits . . . . . . . . . . . . . . 42
Table 61. RxSelReg register (address 17h); reset value:
84h, 10000100b. . . . . . . . . . . . . . . . . . . . . . . . 44
Table 62. Description of RxSelReg bits . . . . . . . . . . . . . . 44
Table 63. RxThresholdReg register (address 18h); reset
value: 84h, 10000100b . . . . . . . . . . . . . . . . . . 44
Table 64. Description of RxThresholdReg bits . . . . . . . . 44
Table 65. DemodReg register (address 19h); reset value:
4Dh, 01001101b. . . . . . . . . . . . . . . . . . . . . . . . 45
Table 66. Description of DemodReg bits . . . . . . . . . . . . . 45
Table 67. FelNFC1Reg register (address 1Ah); reset value:
00h, 00000000b. . . . . . . . . . . . . . . . . . . . . . . . 46
Table 68. Description of FelNFC1Reg bits . . . . . . . . . . . 46
Table 69. FelNFC2Reg register (address1Bh); reset value:
00h, 00000000b. . . . . . . . . . . . . . . . . . . . . . . . 47
Table 70. Description of FelNFC2Reg bits . . . . . . . . . . . 47
T
able 71. MifNFCReg register (address 1Ch); reset value:
62h, 01100010b . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 72. Description of MifNFCReg bits. . . . . . . . . . . . . 48
Table 73. ManualRCVReg register (address 1Dh); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 49
Table 74. Description of ManualRCVReg bits . . . . . . . . . 49
Table 75. TypeBReg register (address 1Eh); reset value:
00h, 00000000b. . . . . . . . . . . . . . . . . . . . . . . . 50
Table 76. Description of TypeBReg bits. . . . . . . . . . . . . . 50
Table 77. SerialSpeedReg register (address 1Fh); reset
value: EBh, 11101011b . . . . . . . . . . . . . . . . . . 51