Datasheet

PN512 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352 120 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
Remark: For separated address and data bus the signal ALE is not relevant and the
multiplexed addresses on the data bus don’t care.
For the multiplexed address and data bus the address lines A0 to A3 have to be
connected as described in chapter Automatic host controller Interface Type Detection.
25.2.2.2 Bus timing for common Read/Write strobe
Fig 42. Timing diagram for separated Read/Write strobe
001aan233
t
LHLL
t
CLWL
t
LLWL
t
WHWL
t
WLWH
t
WHWL
t
WHDX
t
RHDZ
t
WLDV
t
RLDV
t
WHCH
t
WHAX
t
AVLL
t
LLAX
t
AVWL
ALE
NCS
NWR
NRD
D0...D7 D0...D7
A0...A3
multiplexed
addressbus
A0...A3
SEPARATED ADDRESSBUS A0...A3
Table 174. Timing specification for common Read/Write strobe
Symbol Parameter Min Max Unit
t
LHLL
AS pulse width 10 - ns
t
AVLL
Multiplexed Address Bus valid to AS low (Address Set Up Time) 5 - ns
t
LLAX
Multiplexed Address Bus valid after AS low (Address Hold Time) 5 - ns
t
LLSL
AS low to NDS low 10 - ns
t
CLSL
NCS low to NDS low 0 - ns
t
SHCH
NDS high to NCS high 0 - ns
t
SLDV,R
NDS low to DATA valid (for read cycle) - 35 ns
t
SHDZ
NDS low to DATA high impedance (read cycle) - 10 ns
t
DVSH
DATA valid to NDS high (for write cycle) 5 - ns
t
SHDX
DATA hold after NDS high (write cycle, Hold Time) 5 - ns
t
SHRX
R/NW hold after NDS high 5 - ns
t
SLSH
NDS pulse width 40 - ns
t
AVSL
Separated Address Bus valid to NDS low (Hold Time) 30 - ns
t
SHAX
Separated Address Bus valid after NDS high (Set Up Time) 5 - ns