Datasheet

PN512 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352 119 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
25.2 8-bit parallel interface timing
25.2.1 AC symbols
Each timing symbol has five characters. The first character is always 't' for time. The other
characters indicate the name of a signal or the logic state of that signal (depending on
position):
Example: t
AVLL
= time for address valid to ALE low
25.2.2 AC operating specification
25.2.2.1 Bus timing for separated Read/Write strobe
Table 172. AC symbols
Designation Signal Designation Logic Level
A address H HIGH
D data L LOW
W NWR or nWait Z high impedance
R NRD or R/NW or nWrite X any level or data
L ALE or AS V any valid signal or data
C NCS N NSS
S NDS or nDStrb and nAStrb, SCK
Table 173. Timing specification for separated Read/Write strobe
Symbol Parameter Min Max Unit
t
LHLL
ALE pulse width 10 - ns
t
AVLL
Multiplexed Address Bus valid to ALE low (Address Set Up Time) 5 - ns
t
LLAX
Multiplexed Address Bus valid after ALE low (Address Hold Time) 5 - ns
t
LLWL
ALE low to NWR, NRD low 10 - ns
t
CLWL
NCS low to NRD, NWR low 0 - ns
t
WHCH
NRD, NWR high to NCS high 0 - ns
t
RLDV
NRD low to DATA valid - 35 ns
t
RHDZ
NRD high to DATA high impedance - 10 ns
t
DVWH
DATA valid to NWR high 5 - ns
t
WHDX
DATA hold after NWR high (Data Hold Time) 5 - ns
t
WLWH
NRD, NWR pulse width 40 - ns
t
AVWL
Separated Address Bus valid to NRD, NWR low (Set Up Time) 30 - ns
t
WHAX
Separated Address Bus valid after NWR high (Hold Time) 5 - ns
t
WHWL
period between sequenced read/write accesses 40 - ns