Datasheet

PN512 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352 117 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
25.1 Timing characteristics
Fig 39. Pin RX input voltage range
001aak012
VMID
0 V
V
mod
V
i(p-p)(max)
V
i(p-p)(min)
13.56 MHz
carrier
Table 170. SPI timing characteristics
Symbol Parameter Conditions Min Typ Max Unit
t
WL
pulse width LOW line SCK 50 - - ns
t
WH
pulse width HIGH line SCK 50 - - ns
t
h(SCKH-D)
SCK HIGH to data input
hold time
SCK to changing
MOSI
25 - - ns
t
su(D-SCKH)
data input to SCK HIGH
set-up time
changing MOSI to
SCK
25 - - ns
t
h(SCKL-Q)
SCK LOW to data output
hold time
SCK to changing
MISO
- - 25 ns
t
(SCKL-NSSH)
SCK LOW to NSS HIGH
time
0- - ns
Table 171. I
2
C-bus timing in Fast mode
Symbol Parameter Conditions Fast mode High-speed
mode
Unit
Min Max Min Max
f
SCL
SCL clock frequency 0 400 0 3400 kHz
t
HD;STA
hold time (repeated) START
condition
after this period,
the first clock pulse
is generated
600 - 160 - ns
t
SU;STA
set-up time for a repeated
START condition
600 - 160 - ns
t
SU;STO
set-up time for STOP condition 600 - 160 - ns
t
LOW
LOW period of the SCL clock 1300 - 160 - ns
t
HIGH
HIGH period of the SCL clock 600 - 60 - ns
t
HD;DAT
data hold time 0 900 0 70 ns